3rd annual symposium on theoretical aspects of computer science on STACS 86
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Study of IDDQ Subset Selection Algorithms for Bridging Faults
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Fault Simulation of IDDQ Tests for Bridging Faults in Sequential Circuits
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Compact test generation for bridging faults under I/sub DDQ/ testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IC test using the energy consumption ratio
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fault models and test generation for IDDQ testing: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Reducing fault dictionary size for million-gate large circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified submodular framework for multimodal IC Trojan detection
IH'10 Proceedings of the 12th international conference on Information hiding
| Hi-index | 14.98 |
In the absence of information about the layout, test generation, and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating IDDQTests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that: The problem of computing IDDQ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable; and, even under some pessimistic assumptions, a complete IDDQ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.