Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Algorithms for IDDQ measurement based diagnosis of bridging faults
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
A Study of IDDQ Subset Selection Algorithms for Bridging Faults
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits
IEEE Transactions on Computers
Bridging Faults in Pipelined Circuits
Journal of Electronic Testing: Theory and Applications
Fast Algorithms for Computer IDDQ Tests for Combination Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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Abstract: The notion of indistinguishable pairs is introduced. Two methods to compute such pairs-an explicit scheme and an implicit scheme-are presented. The resulting fault simulation algorithms, list-based scheme and tree-based scheme are compared using a variety of faultlists and test sets. The performance of the tree-based scheme is found to be superior to the list-based scheme. Applications where the list-based scheme perform better are discussed.