Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fault Simulation of IDDQ Tests for Bridging Faults in Sequential Circuits
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Compact test generation for bridging faults under I/sub DDQ/ testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A study of IDDQ subset selection algorithms for bridging faults
ITC'94 Proceedings of the 1994 international conference on Test
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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A system to generate IDDQ tests for bridging faults (BFs) and leakage faults in combinational CMOS circuit is de-scribed. Experimental results for different sets of BFs demonstrates the efficiency and flexibility of the approach.