Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Fault simulation for general FCMOS ICs
Journal of Electronic Testing: Theory and Applications
Dynamic effects in the detection of bridging faults in CMOS ICs
Journal of Electronic Testing: Theory and Applications
Bridging defects resistance in the metal layer of a CMOS process
Journal of Electronic Testing: Theory and Applications
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
BART: A Bridging Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
On the performance of level-clocked circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Iddq Testing for High Performance CMOS - The Next Ten Years
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Voting model based diagnosis of bridging faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Micropipeline Architecture for Multiplier-less FIR Filters
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Fault Simulation of IDDQ Tests for Bridging Faults in Sequential Circuits
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and Iddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case.