A timing analysis of level-clocked circuitry
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
IEEE Transactions on Computers
Timing in level-clocked circuits
Timing in level-clocked circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Edge-triggering vs. two-phase level-clocking
Proceedings of the 1993 symposium on Research on integrated systems
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
Algorithms for retiming level-clocked circuits and their use in increased circuit robustness
Algorithms for retiming level-clocked circuits and their use in increased circuit robustness
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming gated-clocks and precharged circuit structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Bridging Faults in Pipelined Circuits
Journal of Electronic Testing: Theory and Applications
Optimization of synchronous circuits
Logic Synthesis and Verification
Clock schedule verification with crosstalk
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Timing Verification with Crosstalk for Transparently Latched Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Clock schedule verification under process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Binning optimization based on SSTA for transparently-latched circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Although it is well-known that substituting level-sensitive latches for edge-triggered registers can boost circuit performance, results of measuring the performance gained by using latches in real circuits-when retiming is used to optimize the performance of both types of circuits-have been disappointing. In this paper we re-examine the speedup that can be expected from using latches and develop upper and lower bounds on the clock period of retimed circuits that are tighter than previously published bounds. We then show experimentally that pipelined level-clocked circuits almost always achieve the lower bound while edge-clocked circuits seldom do. These bounds also illuminate where performance from level-clocking can and cannot be achieved. For the circuits that do benefit from latches, the average speedup is about 11%, although much greater speedups are common. Another factor affecting performance that has generally been ignored is clock skew. Clocks in edge-clocked circuits must be slowed down by an amount equal to the clock skew while level-clocked circuits are more tolerant of clock skew. We show experimentally that on average level-clocked circuits can tolerate clock skew of 15% of the clock period which can be translated directly into increased performance.