Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
A faster strongly polynomial minimum cost flow algorithm
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Computation structures
Introduction to algorithms
Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
A timing analysis of level-clocked circuitry
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Edge-triggering vs. two-phase level-clocking
Proceedings of the 1993 symposium on Research on integrated systems
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Retiming of Circuits with Single Phase Transparent Latches
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
DAC '83 Proceedings of the 20th Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Minimum area retiming with equivalent initial states
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Asymptotically efficient retiming under setup and hold constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Minimizing sensitivity to delay variations in high-performance synchronous circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Maximizing performance by retiming and clock skew scheduling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient minarea retiming of large level-clocked circuits
Proceedings of the conference on Design, automation and test in Europe
On the performance of level-clocked circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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