The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems
IEEE Transactions on Computers
A mixed-integer linear programming problem which is efficiently solvable
Journal of Algorithms
Computation structures
Introduction to algorithms
Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
A timing analysis of level-clocked circuitry
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
IEEE Transactions on Computers
Timing in level-clocked circuits
Timing in level-clocked circuits
Edge-triggering vs. two-phase level-clocking
Proceedings of the 1993 symposium on Research on integrated systems
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
A timing analysis and optimization system for level-clocked circuitry
A timing analysis and optimization system for level-clocked circuitry
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Linear Programming in Linear Time When the Dimension Is Fixed
Journal of the ACM (JACM)
Introduction to VLSI Systems
Retiming of Circuits with Single Phase Transparent Latches
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ON RETIMING SYNCHRONOUS CIRCUITRY AND MIXED-INTEGER OPTIMIZATION
ON RETIMING SYNCHRONOUS CIRCUITRY AND MIXED-INTEGER OPTIMIZATION
Asymptotically efficient retiming under setup and hold constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Minimizing sensitivity to delay variations in high-performance synchronous circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Maximizing performance by retiming and clock skew scheduling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register Transformations with Multiple Clock Domains
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Timing optimization by replacing flip-flops to latches
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Spec-based flip-flop and latch repeater planning
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.02 |