A timing analysis of level-clocked circuitry
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A verification technique for gated clock
DAC '93 Proceedings of the 30th international Design Automation Conference
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
A timing analysis algorithm for circuits with level-sensitive latches
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An algorithm for incremental timing analysis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Identification of critical paths in circuits with level-sensitive latches
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Verification
Clock schedule verification with crosstalk
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
From max-plus algebra to nonexpansive mappings: a nonlinear theory for discrete event systems
Theoretical Computer Science
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip
Discrete Applied Mathematics
Timing Verification with Crosstalk for Transparently Latched Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Clock schedule verification under process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Globally optimal solutions of max---min systems
Journal of Global Optimization
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