IEEE Transactions on Computers
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Critical paths in circuits with level-sensitive latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
A timing analysis algorithm for circuits with level-sensitive latches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Delay insertion method in clock skew scheduling
Proceedings of the 2005 international symposium on Physical design
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This paper describes a linear programming (LP) formulation for performance optimization of large-scale, synchronous circuits with level-sensitive latches. The proposed formulation permits circuits to operate at a higher clock frequency---that is, with a lower clock period---by the application of both non-zero clock skew scheduling [7] and time borrowing [9]. This LP formulation is computationally efficient and demonstrates significant circuit performance improvement. Unlike the approach documented in [2], the LP model of the clock period minimization problem presented here is stand-alone and independent of the specific LP solver (solution algorithm) used. The modified big M (MBM) method is introduced and applied to the linearization of the non-linear timing constraints of level-sensitive circuits into a solvable set of fully linear constraints. Clock period improvements as large as 63% are demonstrated over conventional flip-flop based circuits with zero clock skew. These improvements are shown on the ISCAS'89 benchmark circuits by using the industrial linear solver CPLEX [1].