Timing optimization through clock skew scheduling

Scaling trends of on-chip Power distribution noise

SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Testing Clock Distribution Circuits Using an Analytic Signal Method

ITC '01 Proceedings of the 2001 IEEE International Test Conference

A clock-tuning circuit for system-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Clock Scheduling and Clocktree Construction for High Performance ASICS

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Scaling trends of on-chip power distribution noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Delay insertion method in clock skew scheduling

Proceedings of the 2005 international symposium on Physical design

Effects of process and environmental variations on timing characteristics of clocked registers

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Efficient incremental clock latency scheduling for large circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

Clock skew scheduling with race conditions considered

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Analog Integrated Circuits and Signal Processing

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

Proceedings of the 45th annual Design Automation Conference

Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction

Proceedings of the 45th annual Design Automation Conference

Custom topology rotary clock router with tree subnetworks

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Parameter variation effects on timing characteristics of high performance clocked registers

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation