Parameter variation effects on timing characteristics of high performance clocked registers

Authors:
William R. Roberts;Dimitrios Velenis
Affiliations:
Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL;Electrical and Computer Engineering Department, Illinois Institute of Technology, Chicago, IL
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to parameter variations is demonstrated for four different register designs. The robustness of each register design under variations in power supply voltage, temperature, and gate oxide thickness is determined.