Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 37th Annual Design Automation Conference
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections
Integration, the VLSI Journal
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
Process Variations and their Impact on Circuit Operation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Design of Clock Distribution Networks in Presence of Process Variations
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effects of process and environmental variations on timing characteristics of clocked registers
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Timing-driven variation-aware nonuniform clock mesh synthesis
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parameter variation effects on timing characteristics of high performance clocked registers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks
Integration, the VLSI Journal
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The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A polynomial time algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay to the most critical data paths. Strategies for enhancing the physical layout of the clock tree to decrease delay uncertainty are also presented. Application of the methodology on benchmark circuits demonstrates clock tree topologies with decreased delay uncertainties of up to 90%. Techniques to enhance a clock tree layout have been applied on a set of benchmark circuits, yielding a reduction in delay uncertainty of up to 48%.