Investigations of fault-tolerant networks of computers
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Polymorphic-Torus Architecture for Computer Vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
An Upper Bound on Expected Clock Skew in Synchronous Systems
IEEE Transactions on Computers
Four State Asynchronous Architectures
IEEE Transactions on Computers
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
Properties of Generalized Branch and Combine Clock Networks
IEEE Transactions on Parallel and Distributed Systems
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
IEEE Transactions on Parallel and Distributed Systems
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
VHDL Modeling of Optoelectronic Interconnect Networks
Analog Integrated Circuits and Signal Processing - Special issue: Analog VHDL
Parallel preprocessing and postprocessing in finite-element analysis on a multiprocessor computer
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Statistical skew modeling for general clock distribution networks in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound
IEEE Transactions on Parallel and Distributed Systems
Packet Synchronization for Synchronous Optical Deflection-Routed Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Theory of Generalized Branch and Combine Clock Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Paper: Hybrid systolic sorters
Parallel Computing
Pipelining communications in large VLSI/ULSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitable problem of clock skews and delays, which can be especially acute in VLSI systems as feature sizes shrink. For the near term, good engineering and technology improvements can be expected to maintain the feasibility of clocking in such systems; however, clock distribution problems crop up in any technology as systems grow. An alternative means of enforcing necessary synchronization is the use of self-timed asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best possible synchronization schemes for large processor arrays are proposed.