Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Sorting on a mesh-connected parallel computer
Communications of the ACM
Introduction to VLSI Systems
Systolic (VLSI) arrays for relational database operations
SIGMOD '80 Proceedings of the 1980 ACM SIGMOD international conference on Management of data
Bitonic Sort on a Mesh-Connected Parallel Computer
IEEE Transactions on Computers
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
IEEE Transactions on Computers
Fully Interconnecting Multiple Computers with Pipelined Sorting Nets
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
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Area performance of systolic sorters is investigated by introducing the river routing model. Three kinds of systolic sorters; Batcher's bitonic sort, Stone's shuffle sort, and odd-even transposition sort on a mesh-connected array, are discussed. It is pointed out that the area performance of systolic sorters is dominated by wiring space between cells. To remedy the synchronization problem due to the clock skew, a hybrid sorter and a recirculating hybrid sorter are proposed here. It is confirmed that the recirculating hybrid sorter is reconfigurable and suitable for WSI implementation.