The VLSI Complexity of Sorting
IEEE Transactions on Computers
The architecture of MANIP: a parallel computer system for solving NP-complete problems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Paper: Hybrid systolic sorters
Parallel Computing
VLSI Sorting with Reduced Hardware
IEEE Transactions on Computers
Hi-index | 14.99 |
A pipelined multiprocessor interconnection method functionally equivalent to a full crossbar, but with a per processor cost proportional to the square of the log of the total number of processors, is presented.