VLSI Sorting with Reduced Hardware

Authors:
Joseph Ja'Ja';Robert Michael Owens
Affiliations:
Department of Computer Science, Pennsylvania State University, University Park, PA 16802./ Department of Electrical Engineering, University of Maryland, College Park, MD 20742.;Department of Computer Science, Pennsylvania State University, University Park, PA 16802.
Venue:
IEEE Transactions on Computers
Year:
1984

Citing 13
Cited 1

Bounds to Complexities of Networks for Sorting and for Switching

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The cube-connected cycles: a versatile network for parallel computation

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Sorting on a mesh-connected parallel computer

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Introduction to VLSI Systems

Introduction to VLSI Systems
A model of computation for VLSI with related complexity results

STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A complexity theory for VLSI

A complexity theory for VLSI
Bitonic Sort on a Mesh-Connected Parallel Computer

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Parallel Processing with the Perfect Shuffle

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On the Complexity of Sorting in Magnetic Bubble Memory Systems

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Fully Interconnecting Multiple Computers with Pipelined Sorting Nets

IEEE Transactions on Computers
The VLSI Complexity of Sorting

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Sorting networks and their applications

AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Algorithm and hardware for a merge sort using multiple processors

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The arithmetic cube

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Abstract

We propose a new VLSI architecture which allows many problems to be solved quite efficiently on chips with very small processing areas. We consider in detail the sorting problem and show how it can be solved quickly and elegantly on our model. We show that sorting n numbers can be done on a chip with processing area A = o(n) with an almost optimal speedup in a network with mesh-connected interconnections. The control is shown to be simple and easily implementable in VLSI.