Algorithm and hardware for a merge sort using multiple processors

Authors:
S. Todd
Affiliations:
IBM United Kingdom Scientific Center, Peterlee, Durham, England
Venue:
IBM Journal of Research and Development
Year:
1978

Citing 2
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Abstract

An algorithm is described that allows log (n) processors to sort n records in just over 2n write cycles, together with suitable hardware to support the algorithm. The algorithm is a parallel version of the straight merge sort. The passes of the merge sort are run overlapped, with each pass supported by a separate processor. The intermediate files of a serial merge sort are replaced by first-in first-out queues. The processors and queues may be implemented in conventional solid logic technology or in bubble technology. A hybrid technology is also appropriate.