Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
VLSI array processors
Vector quantization and signal compression
Vector quantization and signal compression
Sequencer-based data path synthesis of regular iterative algorithms
DAC '94 Proceedings of the 31st annual Design Automation Conference
VLSI architectures for vector quantization
Journal of VLSI Signal Processing Systems
Scalability of Programmable FIR Digital Filters
Journal of VLSI Signal Processing Systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Introduction to Parallel Processing: Algorithms and Architectures
Introduction to Parallel Processing: Algorithms and Architectures
Source Coding Theory
Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
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Current and future requirements for adaptive real-time image compression challenge even the capabilities of highly parallel realizations in terms of hardware performance. Previously proposed linear array structures for full-search vector quantization do not offer scalability and adaptivity in this context, because they require separate data/control pins for dynamically updating the codevectors and complicated interlock mechanisms to ensure that the regular data flow is not corrupted as a result of updates. We explore the design space for full-search vector quantizers and propose a novel linear processor array architecture in which global wiring is limited to clock and power supply distribution, thus allowing high-speed processing in spite of only limited communication with the host via the boundary processors. The resulting fully pipelined design is not only area-efficient for VLSI implementation but is also readily scalable and offers extremely high performance.