Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
VLSI on-chip interconnection performance simulations and measurements
IBM Journal of Research and Development
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
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Previous designs of programmable FIR digital filters havedemonstrated that the use of broadcast data and control can lead to ahigh performance-to-cost ratio. As the technology advances to thedeep sub-micrometer regime, such an approach should be re-examined bytaking the effect of interconnections into account. In this paper, weshow that the contribution of interconnect delay to the cycle time isno longer negligible and will hamper the scalability of suchbroadcast designs. Further speed and density improvements throughscaling can be secured by the fully pipelined design in which bothdata and control signals are restricted to localconnections.