Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations

Authors:
Ioannis Stamoulias;Elias S. Manolakos
Affiliations:
National & Kapodistrian University of Athens, Greece;National & Kapodistrian University of Athens, Greece
Venue:
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Year:
2013

Citing 10
Cited 0

VLSI array processors

VLSI array processors
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization

Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
A Systolic Algorithm for the k-Nearest Neighbors Problem

IEEE Transactions on Computers
Pattern Classification (2nd Edition)

Pattern Classification (2nd Edition)
A novel prostate cancer classification technique using intermediate memory tabu search

EURASIP Journal on Applied Signal Processing
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA implementation of kNN classifier based on wavelet transform and partial distance search

SCIA'07 Proceedings of the 15th Scandinavian conference on Image analysis
BLAS Comparison on FPGA, CPU and GPU

ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
GPU Versus FPGA for High Productivity Computing

FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Knowledge discovery approach to automated cardiac SPECT diagnosis

Artificial Intelligence in Medicine

Quantified Score

Hi-index	0.00

Visualization

Abstract

We designed a variety of k-nearest-neighbor parallel architectures for FPGAs in the form of parameterizable soft IP cores. We show that they can be used to solve large classification problems with thousands of training vectors, or thousands of vector dimensions using a single FPGA, and achieve very high throughput. They can be used to flexibly synthesize architectures that also cover: 1NN classification (vector quantization), multishot queries (with different k), LOOCV cross-validation, and compare favorably to GPU implementations. To the best of our knowledge this is the first attempt to design flexible IP cores for the popular kNN classifier.