FPGA implementation of kNN classifier based on wavelet transform and partial distance search

Authors:
Yao-Jung Yeh;Hui-Ya Li;Wen-Jyi Hwang;Chiung-Yao Fang
Affiliations:
Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan
Venue:
SCIA'07 Proceedings of the 15th Scandinavian conference on Image analysis
Year:
2007

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Abstract

A novel algorithm for field programmable gate array (FPGA) realization of kNN classifier is presented in this paper. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the partial distance search (PDS) in the wavelet domain. It employs subspace search, bitplane reduction and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of kNN classification systems where both high throughput and low area cost are desired.