Introduction to the theory of neural computation
Introduction to the theory of neural computation
Vector quantization and signal compression
Vector quantization and signal compression
Analog VLSI Circuits for Competitive Learning Networks
Analog Integrated Circuits and Signal Processing - Special issue: cellular neural networks and analog VLSI
ACM Computing Surveys (CSUR)
A novel competitive learning algorithm for the parametric classification with Gaussian distributions
Pattern Recognition Letters
Self-Organizing Maps
Learning patterns in wireless sensor networks based on wavelet neural networks
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
Parallel competitive learning algorithm for fast codebook design on partitioned space
CLUSTER '04 Proceedings of the 2004 IEEE International Conference on Cluster Computing
Competitive Learning Techniques for Color Image Segmentation
CISP '08 Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 3 - Volume 03
MapReduce for Data Intensive Scientific Analyses
ESCIENCE '08 Proceedings of the 2008 Fourth IEEE International Conference on eScience
High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware
IEA/AIE '09 Proceedings of the 22nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: Next-Generation Applied Intelligence
FPGA implementation of kNN classifier based on wavelet transform and partial distance search
SCIA'07 Proceedings of the 15th Scandinavian conference on Image analysis
IterativeSOMSO: an iterative self-organizing map for spatial outlier detection
ISNN'10 Proceedings of the 7th international conference on Advances in Neural Networks - Volume Part I
Competitive learning algorithms for robust vector quantization
IEEE Transactions on Signal Processing
A new VLSI architecture for full-search vector quantization
IEEE Transactions on Circuits and Systems for Video Technology
Modular VLSI architectures for real-time full-search-based vector quantization
IEEE Transactions on Circuits and Systems for Video Technology
Self-organizing maps, vector quantization, and mixture modeling
IEEE Transactions on Neural Networks
Rival penalized competitive learning for clustering analysis, RBF net, and curve detection
IEEE Transactions on Neural Networks
| Hi-index | 0.00 |
This paper presents a novel pipelined architecture for competitive learning (CL). The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for reducing the computation time. In the architecture, a novel codeword swapping scheme is adopted so that neuron competitions for different training vectors can be operated concurrently. The neuron updating process is based on a hardware divider with simple table lookup operations. The divider performs finite precision calculations for area cost reduction at the expense of slight degradation in training performance. The CPU time of the NIOS processor executing the CL training with the proposed architecture as an accelerator is measured. Experimental results show that the NIOS processor with the proposed architecture as an accelerator can achieve up to a speedup of 254 over its software counterpart running on a general purpose processor Pentium IV without hardware support.