FPGA implementation of full-search vector quantization based on partial distance search
Microprocessors & Microsystems
Accelerating VQ-based codeword search on the basis of partial search strategy
Computer Standards & Interfaces
High speed c-means clustering in reconfigurable hardware
Microprocessors & Microsystems
Efficient pipelined architecture for competitive learning
Journal of Parallel and Distributed Computing
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Vector quantization (VQ) has become feasible to be employed for real-time applications by using VLSI technology. In this paper, the authors propose modular linearly connected VLSI architectures for VQ that can support real-time image processing applications. Each processing element in the design consists of an adder and a shift register instead of a multiplier. The designs require fixed I/O bandwidth with the host and allow codebook changes. The throughput is independent of the codebook size. These designs can be extended to the case when a fixed number of processors are available. A number of VQ schemes-single-stage and multistage VQ, classified VQ, etc.-can be implemented using this approach