Vector quantization and signal compression
Vector quantization and signal compression
Wavelets and subband coding
A new VLSI architecture for full-search vector quantization
IEEE Transactions on Circuits and Systems for Video Technology
Modular VLSI architectures for real-time full-search-based vector quantization
IEEE Transactions on Circuits and Systems for Video Technology
Digital implementation of hierarchical vector quantization
IEEE Transactions on Neural Networks
Microprocessors & Microsystems
Efficient K-Means VLSI Architecture for Vector Quantization
SCIA '09 Proceedings of the 16th Scandinavian Conference on Image Analysis
High speed c-means clustering in reconfigurable hardware
Microprocessors & Microsystems
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This paper presents a novel algorithm for field programmable gate array (FPGA) realization of vector quantizer (VQ) encoders using partial distance search (PDS). In most applications, the PDS is adopted as a software approach for attaining moderate codeword search acceleration. In this paper, a novel PDS algorithm well suited for hardware realization is proposed. The algorithm employs subspace search, bitplane reduction, and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. Concurrent encoding of different input vectors for further computation acceleration is also allowed by the employment of multiple-module PDS. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of VQ encoding systems where both high throughput and high fidelity are desired.