Vector quantization and signal compression
Vector quantization and signal compression
Speech recognition chip for monosyllables
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Intelligent Internet Search Applications Based on VLSI Associative Processors
SAINT '02 Proceedings of the 2002 Symposium on Applications and the Internet
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Hardware Accelerated Data Analysis
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
2005 Special issue: FPGA implementation of self organizing map with digital phase locked loops
Neural Networks - 2005 Special issue: IJCNN 2005
FPGA implementation of full-search vector quantization based on partial distance search
Microprocessors & Microsystems
VLSI architecture for motion vector quantization
IEEE Transactions on Consumer Electronics
Digital implementation of hierarchical vector quantization
IEEE Transactions on Neural Networks
IP core implementation of a self-organizing neural network
IEEE Transactions on Neural Networks
A massively parallel architecture for self-organizing feature maps
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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This report describes the design of a modular, massive-parallel, neural-network (NN)-based vector quantizer for real-time video coding. The NN is a self-organizing map (SOM) that works only in the training phase for codebook generation, only at the recall phase for real-time image coding, or in both phases for adaptive applications. The neural net can be learned using batch or adaptive training and is controlled by an inside circuit, finite-state machine-based hard controller. The SOM is described in VHDL and implemented on electrically (FPGA) and mask (standard-cell) programmable devices.