Pattern recognition via synchronization in phase-locked loop neural networks
IEEE Transactions on Neural Networks
A new digital pulse-mode neuron with adjustable activation function
IEEE Transactions on Neural Networks
IP core implementation of a self-organizing neural network
IEEE Transactions on Neural Networks
A massively parallel architecture for self-organizing feature maps
IEEE Transactions on Neural Networks
Microprocessors & Microsystems
A Pulse-Coupled Network of SOM
ICONIP '09 Proceedings of the 16th International Conference on Neural Information Processing: Part II
On automatic generation of VHDL code for self-organizing map
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
A dynamically reconfigurable platform for self-organizing neural network hardware
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: models and applications - Volume Part II
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The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small. .