Self-Organizing Maps
2005 Special issue: FPGA implementation of self organizing map with digital phase locked loops
Neural Networks - 2005 Special issue: IJCNN 2005
IP core implementation of a self-organizing neural network
IEEE Transactions on Neural Networks
A massively parallel architecture for self-organizing feature maps
IEEE Transactions on Neural Networks
A dynamically reconfigurable platform for self-organizing neural network hardware
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: models and applications - Volume Part II
| Hi-index | 0.00 |
Self-organizing map (SOM) proposed by T. Kohonen is a neural network with unsupervised leaning to classify multi-dimensional vectors. The performance of SOM implemented in software decreases as the number of neurons increases. Therefore, performance acceleration of SOM by custom hardware is highly desired. In addition the hardware implementation can make the best use of the parallelism embedded in the SOM algorithm. VHSIC hardware description language (VHDL) is widely used to describe and design digital hardware but the VHDL description becomes larger in proportion to the size of SOMe This paper discusses the automatic generation of VHDL description of the hardware SOM by software. A hardware SOM generator is developed and its preliminary results are presented.