Self-Organizing Maps
2005 Special issue: FPGA implementation of self organizing map with digital phase locked loops
Neural Networks - 2005 Special issue: IJCNN 2005
On automatic generation of VHDL code for self-organizing map
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Implementation of artificial neural networks on a reconfigurable hardware accelerator
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
A massively parallel architecture for self-organizing feature maps
IEEE Transactions on Neural Networks
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In this paper, we propose a dynamically reconfigurable platform for self-organizing neural network hardware. In the proposed platform, a hardware unit can be handled as a hardware object in object-oriented design. The hardware object is loaded into the FPGA's virtual hardware circuit space, and accelerates the calculation of self-organizing neural networks. We design two types of the distance calculation, a winner-take-all and a rough-winner-take-all virtual hardware circuit as common parts of self-organizing neural networks. By combining them, we realize four types of self-organizing neural network. Experimental results show that the implemented self-organizing neural network hardware achieves about 100 times faster than the software implementation. Besides, the proposed platform can change its learning mode easily as well as the software implementation. Therefore, the proposed platform features both of the speed of hardware and the flexibility of software.