SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Self-organizing maps
Applications of neural networks
The handbook of brain theory and neural networks
Radial basis function networks
The handbook of brain theory and neural networks
A High Performance SOFM Hardware-System
IWANN '97 Proceedings of the International Work-Conference on Artificial and Natural Neural Networks: Biological and Artificial Computation: From Neuroscience to Technology
A Scalable Processor Array for Self-Organizing Feature Maps
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
SOM Hardware with Acceleration Module for Graphical Representation of the Learning Process
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
A Theory of Networks for Approximation and Learning
A Theory of Networks for Approximation and Learning
Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system
Proceedings of the 7th ACM international conference on Computing frontiers
Evolvable block-based neural network design for applications in dynamic environments
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A dynamically reconfigurable platform for self-organizing neural network hardware
ICONIP'10 Proceedings of the 17th international conference on Neural information processing: models and applications - Volume Part II
Efficient FPGA implementation of a knowledge-based automatic speech classifier
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Artificial Intelligence Review
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The hardware implementation of three different artificial neural networks is presented. The basis for the implementation is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementational issues are considered. Especially resource-efficiency and performance of the presented realizations are discussed.