High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
An adaptive fuzzy logic controller: its VLSI architecture and applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Algorithms for High-Level Synthesis
IEEE Design & Test
Efficient MLP Digital Implementation on FPGA
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Implementation of artificial neural networks on a reconfigurable hardware accelerator
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
Self-adaptive neuro-fuzzy inference systems for classification applications
IEEE Transactions on Fuzzy Systems
Neuro-fuzzy rule generation: survey in soft computing framework
IEEE Transactions on Neural Networks
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This paper presents an efficient synchronous pipeline hardware implementation procedure for a neuro-fuzzy (NF) circuit. We decompose the NF circuit into a feedforward circuit and a backpropagation circuit. The concept of pre-calculation to share computation results between the feedforward circuit and backpropagation circuit is introduced to achieve a high throughput rate and low resource usage. A novel pipeline architecture has been adopted to fulfill the concept of pre-calculation. With the unique pipeline architecture, we have successfully enhanced the throughput rate and resource sharing between modules. Particularly, the multiplier usage has been reduced from 7 to 3 and the divider usage from 3 to 1. Finally, we have implemented the NF circuit on FGPA. Our experimental results show a superior performance than that of an asynchronous pipeline design approach and the NF system implemented on MATLAB®.