Abstraction in FPGA implementation of neural networks
NN'08 Proceedings of the 9th WSEAS International Conference on Neural Networks
Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Realizing general MLP networks with minimal FPGA resources
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Efficient FPGA implementation of a knowledge-based automatic speech classifier
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Neural network implementation in reprogrammable FPGA devices – an example for MLP
ICAISC'06 Proceedings of the 8th international conference on Artificial Intelligence and Soft Computing
Hi-index | 0.00 |
The efficiency and the accuracy of a digital feedforward neural networks must be optimized to obtain both high classification rate and minimum area on chip. In this paper an efficient MLP digital implementation. The key features of the hardware implementation are the virtual neuron based architecture and the use of the sinusoidal activation function for the hidden layer. The effectiveness of the proposed solutions has been evaluated developing different FPGA based neural prototypes for the High Energy Physics domain and the automatic Road Sign Recognition domain. The use of the sinusoidal activation function decreases hardware resource employment of about 32% when compared with the standard sigmoid based neuron implementation. The virtual neuron implementation makes efficient the mapping of a neural network into hardware devices since it leads to a significant decreasing of concurrent memory access.