Communications of the ACM - Special issue on parallelism
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
AMT DAP—a processor array in a workstation environment
Computer Systems Science and Engineering
Neurocomputing
Back propagation implementation on the adaptive solutions CNAPS neurocomputer chip
NIPS-3 Proceedings of the 1990 conference on Advances in neural information processing systems 3
Using and designing massively parallel computers for artificial neural networks
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Implementation and performance of an analog nonvolatile neural network
Analog Integrated Circuits and Signal Processing
The book of GENESIS (2nd ed.): exploring realistic neural models with the GEneral NEural SImulation System
VLSI Artificial Neural Networks Engineering
VLSI Artificial Neural Networks Engineering
Neural Networks for Optimization and Signal Processing
Neural Networks for Optimization and Signal Processing
VLSI Design of Neural Networks
VLSI Design of Neural Networks
Neural Networks: Concepts, Applications and Implementations
Neural Networks: Concepts, Applications and Implementations
VLSI Architectures for Neural Networks
IEEE Micro
Adapting Constant Multipliers in a Neural Network Implementation
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A SIMD/Dataflow Architecture for a Neurocomputer for Spike-Processing Neural Networks (NESPINN)
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
FPGA Implementations of Neural Networks
FPGA Implementations of Neural Networks
Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Neurocomputing
Speeding up hardware evolution: a coprocessor for evolutionary algorithms
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Evolvable block-based neural network design for applications in dynamic environments
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Implementation of artificial neural networks on a reconfigurable hardware accelerator
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
Some computer organizations and their effectiveness
IEEE Transactions on Computers
Analog electronic cochlea design using multiplexing switched-capacitor circuits
IEEE Transactions on Neural Networks
Pulse-stream VLSI neural networks mixing analog and digital techniques
IEEE Transactions on Neural Networks
A programmable analog neural network processor
IEEE Transactions on Neural Networks
An analog VLSI chip emulating sustained and transient response channels of the vertebrate retina
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
The design of a neuro-microprocessor
IEEE Transactions on Neural Networks
A CMOS analog adaptive BAM with on-chip learning and weight refreshing
IEEE Transactions on Neural Networks
POPART: partial optical implementation of adaptive resonance theory 2
IEEE Transactions on Neural Networks
Fast neural net simulation with a DSP processor array
IEEE Transactions on Neural Networks
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The aim of this paper is to propose a new classification approach of artificial neural networks hardware. Our motivation behind this work is justified by the following two arguments: first, during the last two decades a lot of approaches have been proposed for classification of neural networks hardware. However, at present there is not a clear consensus on classification criteria and performances. Second, with the evolution of the microelectronic technology and the design tools and techniques, new artificial neural networks (ANNs) implementations have been proposed, but they are not taken into consideration in the existing classification approaches of ANN hardware. In this paper, we propose a new approach for classification of neural networks hardware. The paper is organized in three parts: in the first part we review most of existing approaches proposed in the literature during the period 1990---2010 and show the advantages and disadvantages of each one. In the second part, we propose a new classification approach that takes into account most of consensual elements in one hand and in the other hand it takes into consideration the evolution of the design technology of integrated circuits and the design techniques. In the third part, we review examples of neural hardware achievements from industrial, academic and research institutions. According to our classification approach, these achievements range from standard chips to VLSI ASICs, FPGA and embedded systems on chip. Finally, we enumerate design issues that are still posed. This could help to give new directions for future research work.