A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
Towards an Artificial Neural Network Framework
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
Evolvable block-based neural network design for applications in dynamic environments
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Artificial Intelligence Review
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This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor resides in the configurable logic, it can execute common genetic operators like crossover and mutation with a targeted data throughput of 420 MByte/s. Together with the microprocessor core, a complex evolutionary algorithm can be developed in software, but is processed at the speed of dedicated hardware.