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An electrically trainable artificial neural network (ETANN) with 10240 “Floating Gate” synapses
Artificial neural networks
Neural network implementation using reconfigurable architectures
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Competitive Learning Algorithms and Neurocomputer Architecture
IEEE Transactions on Computers
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing
IEEE Transactions on Computers
Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Finite Precision Error Analysis of Neural Network Hardware Implementations
IEEE Transactions on Computers
FPGA Implementation of an Adaptable-Size Neural Network
ICANN 96 Proceedings of the 1996 International Conference on Artificial Neural Networks
Artificial Neural Network Implementation on a Fine-Grained FPGA
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
FPGA Implementation of a Neural Network for a Real-Time Hand Tracking System
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Networked FPGA-Based Hardware Implementation of a Neural Network Application
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Theoretical and Implementation Aspects of Pulse Streams: an Overview
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
An Evolvable Hardware Chip for Prosthetic Hand Controller
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
Digital Hardware Realization of a Hyper Basis Function Network for On
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
PI '99 Proceedings of the The 6th International Conference on Parallel Interconnects
A Full-Parallel Digital Implementation for Pre-Trained NNs
IJCNN '00 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 2 - Volume 2
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
NeuroFPGA -- Implementing Artificial Neural Networks on Programmable Logic Devices
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Speeding up hardware evolution: a coprocessor for evolutionary algorithms
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Implementation of artificial neural networks on a reconfigurable hardware accelerator
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
IEEE Transactions on Neural Networks
Guest editorial - Special issue on neural networks hardware implementations
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Analysis and Simulation of a Mixed-Mode Neuron Architecture for Sensor Conditioning
IEEE Transactions on Neural Networks
Block-Based Neural Networks for Personalized ECG Signal Classification
IEEE Transactions on Neural Networks
Artificial Intelligence Review
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Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.