Competitive Learning Algorithms and Neurocomputer Architecture

  • Authors:
  • H. C. Card;G. K. Rosendahl;D. K. McNeill;R. D. McLeod

  • Affiliations:
  • Univ. of Manitoba, Winnipeg, Canada;Univ. of Manitoba, Winnipeg, Canada;Univ. of Manitoba, Winnipeg, Canada;Univ. of Manitoba, Winnipeg, Canada

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1998

Quantified Score

Hi-index 14.98

Visualization

Abstract

This paper begins with an overview of several competitive learning algorithms in artificial neural networks, including self-organizing feature maps, focusing on properties of these algorithms important to hardware implementations. We then discuss previously reported digital implementations of these networks. Finally, we report a reconfigurable parallel neurocomputer architecture we have designed using digital signal processing chips and field-programmable gate array devices. Communications are based upon a broadcast network with FPGA-based message preprocessing and postprocessing. A small prototype of this system has been constructed and applied to competitive learning in self-organizing maps. This machine is able to model slowly-varying nonstationary data in real time.