The 'Neural' Phonetic Typewriter
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Self-organization and associative memory: 3rd edition
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IEEE Transactions on Computers
Parallel Implementation of Self-Organizing Map on the Partial Tree Shape Neurocomputer
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This chapter focuses on parallel implementations of the Self-Organizing Map (SOM) featuring different levels of parallelism. The basic arithmetic-logical operations of SOM are first reviewed for a consideration of implementation issues such as number precision, memory consumption and time complexity. Mapping involves network, training set, neuron and weight parallelism. Examples of the weight and neuron parallel mappings are given for abstract platforms to conduct general principles. Neuron parallel mapping is considered in great detail as it is the most commonly used approach. A review of implementations is given from supercomputers to VLSI (Very Large Scale Integration) chips with criteria for performance comparison.