Self-organization and associative memory: 3rd edition
Self-organization and associative memory: 3rd edition
The Ring Array Processor: a multiprocessing peripheral for connectionist applications
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Using and designing massively parallel computers for artificial neural networks
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Self-organizing maps
Mapping of SOM and LVQ algorithms on a tree shape parallel computer system
Parallel Computing
Competitive Learning Algorithms and Neurocomputer Architecture
IEEE Transactions on Computers
CBMS '95 Proceedings of the Eighth Annual IEEE Symposium on Computer-Based Medical Systems
Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator
Scientific Programming - Parallel Computing Projects of the Swiss Priority Programme
Fast neural net simulation with a DSP processor array
IEEE Transactions on Neural Networks
Parallel implementation of self-organizing maps
Self-Organizing neural networks
Patch clustering for massive data sets
Neurocomputing
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A parallel mapping of self-organizing map (SOM) algorithm is presented for a partial tree shape neurocomputer (PARNEU). PARNEU is a general purpose parallel neurocomputer that is designed for soft computing applications. Practical scalability and a reconfigurable partial tree network are the main architectural features. The presented neuron parallel mapping of SOM with on-line learning illustrates a parallel winner neuron search and a coordinate transfer that are performed in the partial tree network. Phase times are measured to analyse speedup and scalability of the mapping. The performance of the learning phase in SOM with a four processor PARNEU configuration is about 26 MCUPS and the recall phase performs 30 MCPS. Compared to other mappings done for general purpose neurocomputers, PARNEU's performance is very good.