Self-organizing maps
Competitive Learning Algorithms and Neurocomputer Architecture
IEEE Transactions on Computers
Hardware-Friendly Learning Algorithms for Neural Networks: An Overview
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Encoding of Probabilistic Automata into RAM-Based Neural Networks
IJCNN '00 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 3 - Volume 3
Stochastic Reconfigurable Hardware for Neural Networks
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
The Amsterdam Library of Object Images
International Journal of Computer Vision
A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Neural Networks
Self-organizing learning array
IEEE Transactions on Neural Networks
Handwritten digits recognition improved by multiresolution classifier fusion
IbPRIA'11 Proceedings of the 5th Iberian conference on Pattern recognition and image analysis
Hi-index | 0.00 |
A binary Self Organizing Map (SOM) has been designed and implemented on a Field Programmable Gate Array (FPGA) chip. A novel learning algorithm which takes binary inputs and maintains tri-state weights is presented. The binary SOM has the capability of recognizing binary input sequences after training. A novel tri-state rule is used in updating the network weights during the training phase. The rule implementation is highly suited to the FPGA architecture, and allows extremely rapid training. This architecture may be used in real-time for fast pattern clustering and classification of binary features.