Self-organizing maps
A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation
Journal of Systems Architecture: the EUROMICRO Journal
Color image quantization for frame buffer display
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
Novel fast color reduction algorithm for time-constrained applications
Journal of Visual Communication and Image Representation
A binary self-organizing map and its FPGA implementation
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Journal of Real-Time Image Processing
Mathematics and Computers in Simulation
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Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip's internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density FPGAs with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the FPGA's resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource FPGA with acceptable image quality and frame rate.