A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation
Journal of Systems Architecture: the EUROMICRO Journal
A SOM-based Fuzzy System and Its Application in Handwritten Digits Recognition
MSE '00 Proceedings of the 2000 International Conference on Microelectronic Systems Education
Microprocessors & Microsystems
A novel Kohonen SOM-based image compression architecture suitable for moderate density FPGAs
Image and Vision Computing
A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Signal Processing
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A K-SOM quantizer and its hardware implementation requires a considerable amount of processing time during the learning stage. This results from the fact that a queried pixel which is taken from an input image needs to be tested with all codewords in the codebook. This is done in order to find and update the codeword whose distance is the shortest; i.e. the best matching unit (BMU). The processes are iteratively performed until either all pixels are processed or a quantization error is acceptable. During the learning stage, the learning rate is gradually adjusted to condense the codebook to represent an input image. Several approaches have been proposed to accelerate the processing time during the learning stage ranging from a simple pixel sub-sampling approach to an approach to accelerate the BMU finding process. In this paper, we present a novel approach to terminate the learning stage when the mean square error (MSE) is acceptable. A fast mean square error calculation involving selecting and subsampling pixels is incorporated into the algorithm. The experimental results confirm that the approach outperforms the state-of-the-art hardware K-SOM quantizer in terms of execution time and MSE. This comes in exchange with an additional resources utilization of around 30% on a field programmable gate array platform.