A novel Kohonen SOM-based image compression architecture suitable for moderate density FPGAs

Authors:
W. Kurdthongmee
Affiliations:
Division of Computer Engineering, School of Engineering and Resources Management, Walailak University, 222 Thaibury, Tha-sa-la, Nakorn-si-thammarat 80160, Thailand
Venue:
Image and Vision Computing
Year:
2008

Citing 2
Cited 2

A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation

Journal of Systems Architecture: the EUROMICRO Journal
Novel fast color reduction algorithm for time-constrained applications

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Utilization of a fast MSE calculation approach to improve the image quality and accelerate the operation of a hardware K-SOM quantizer

Microprocessors & Microsystems
Utilization of a rational-based representation to improve the image quality of a hardware-based K-SOM quantizer

Journal of Real-Time Image Processing

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Abstract

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The main drawback of this technique is that it is a very computationally intensive task if software implementation is performed alone. Fortunately, the structure is fairly easy to convert into parallel processing units. However, it consumes much of a microchip's internal resources and results in utilizing more than a single microchip to realize the structure in pure hardware. Previously proposed K-SOM realizations were mainly targeted on implementing on an ASIC (Application Specific Integrated Circuit) with low restriction on resource utilization. In this paper, we, in contrast, propose a novel architecture of K-SOM which compromises between image quality, frame rate throughput and FPGA's resource utilization. The architecture is based on unsigned integer arithmetic in all operations and has been successfully synthesized on a single moderate resource FPGA with acceptable image quality and frame rate.