Scalable architecture for on-chip neural network training using swarm intelligence
Proceedings of the conference on Design, automation and test in Europe
A binary self-organizing map and its FPGA implementation
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
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In this paper, we propose reconfigurable, low-cost andreadily available hardware architecture for an artificialneuron. This is used to build a feed-forward artificialneural network. For this purpose, we use field-programmablegate arrays i.e. FPGAs. However, as thestate-of-the-art FPGAs still lack the gate density necessaryto the implementation of large neural networks ofthousands of neurons, we use a stochastic process toimplement the computation performed by a neuron. Themultiplication an addition of stochastic values is simplyimplemented by an ensemble of XNOR and AND gatesrespectively.