Neural networks: applications in industry, business and science
Communications of the ACM
The roots of backpropagation: from ordered derivatives to neural networks and political forecasting
The roots of backpropagation: from ordered derivatives to neural networks and political forecasting
Handbook of Neural Computation
Handbook of Neural Computation
Finite Precision Error Analysis of Neural Network Hardware Implementations
IEEE Transactions on Computers
Stochastic Reconfigurable Hardware for Neural Networks
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
An Analysis Of PSO Hybrid Algorithms For Feed-Forward Neural Networks Training
SBRN '06 Proceedings of the Ninth Brazilian Symposium on Neural Networks
Neural Networks: A Comprehensive Foundation (3rd Edition)
Neural Networks: A Comprehensive Foundation (3rd Edition)
IEEE Transactions on Neural Networks
Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization
Engineering Applications of Artificial Intelligence
Hardware/software co-design for particle swarm optimization algorithm
Information Sciences: an International Journal
A modular and efficient hardware architecture for particle swarm optimization algorithm
Microprocessors & Microsystems
Neural identification of dynamic systems on FPGA with improved PSO learning
Applied Soft Computing
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This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing field of applications which has been recently used to train neural networks. The architecture exploits PSO algorithm to evolve network weights as well as a method called layer partitioning to implement neural networks. In the proposed method, a neural network is partitioned into groups of neurons and the groups are sequentially mapped to available functional units. Thus, the architecture is reconfigurable for training and implementing different multilayer feedforward neural networks without the need for modifying the architecture. The implementation is intended for real-time applications regarding hardware cost and speed. The results show that the proposed system provides a trade-off between resource requirements and speed.