Neural network fundamentals with graphs, algorithms, and applications
Neural network fundamentals with graphs, algorithms, and applications
FPGA Implementation of an Adaptable-Size Neural Network
ICANN 96 Proceedings of the 1996 International Conference on Artificial Neural Networks
Area Chip Consumption by a Novel Digital CNN Architecture for Pattern Recognition
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Evolvable block-based neural network design for applications in dynamic environments
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Neural network implementation in reprogrammable FPGA devices – an example for MLP
ICAISC'06 Proceedings of the 8th international conference on Artificial Intelligence and Soft Computing
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This paper describes a networked FPGA-based implementation of the FAST (Flexible Adaptable- Size Topology) architecture, an Artificial Neural Network (ANN) that dynamically adapts its size. Most ANN models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices are very well adapted for the implementation of ANN with in-circuit structure adaptation. To realize this implementation we used a network of Labomat 3 boards (a reconfigurable platform developed in our laboratory), which communicate with each other using TCP/IP or a faster, direct hardware connection.