Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation

Authors:
Rafael Gadea;Joaquín Cerdá;Franciso Ballester;Antonio Mocholí
Affiliations:
Department of Electronic Engineering, Universidad Politecnica de Valencia, 46022 Valencia, Spain, rgadea@eln.upv.es;Department of Electronic Engineering, Universidad Politecnica de Valencia, 46022 Valencia, Spain, joacerbo@teleco.upv.es;Department of Electronic Engineering, Universidad Politecnica de Valencia, 46022 Valencia, Spain, fballest@eln.upv.es;Department of Electronic Engineering, Universidad Politecnica de Valencia, 46022 Valencia, Spain, amocholi@eln.upv.es
Venue:
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Year:
2000

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Abstract

The paper describes the implementation of a systolic array for a multilayer perceptron on a Virtex XCV400 FPGA with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. Parallelism is better exploited because both forward and backward phases can be performed simultaneously. We can implement very large interconnection layers by using large Xilinx devices with embedded memories alongside the projection used in the systolic architecture. These physical and architectural features --- together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL --- create an easy, flexible, and fast method of designing a complete ANN on a single FPGA. The result offers a high degree of parallelism and fast performance.