A unified systolic architecture for artificial neural networks
Journal of Parallel and Distributed Computing - Neural Computing
An efficient implementation of the back-propagation algorithm on the connection machine CM-2
Advances in neural information processing systems 2
Introduction to artificial neural systems
Introduction to artificial neural systems
Effects of multiplier output offsets on on-chip learning for analog neuro-chips
Neural Processing Letters
Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Using FPLs to Implement a Reconfigurable Highly Parallel Computer
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
FPGA-Based System Design
Reconfigurable hardware for neural networks: binary versus stochastic
Neural Computing and Applications
ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
XMLP: a Feed-Forward Neural Network with Two-Dimensional Layers and Partial Connectivity
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Artificial neural networks: a review of commercial hardware
Engineering Applications of Artificial Intelligence
Implementation of a neuro-fuzzy network with on-chip learning and its applications
Expert Systems with Applications: An International Journal
An associative memory-based learning model with an efficient hardware implementation in FPGA
Expert Systems with Applications: An International Journal
Iris recognition using artificial neural networks
Expert Systems with Applications: An International Journal
Implementing the induction-motor drive with four-switch inverter: An application of neural networks
Expert Systems with Applications: An International Journal
Financial ratings with scarce information: A neural network approach
Expert Systems with Applications: An International Journal
Expert Systems with Applications: An International Journal
Toward a general-purpose analog VLSI neural network with on-chip learning
IEEE Transactions on Neural Networks
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There are several neural network implementations using either software, hardware-based or a hardware/software co-design. This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP). In this paper, we explore the parallelism of neural networks and allow on-the-fly changes of the number of inputs, number of layers and number of neurons per layer of the net. This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware. In order to reduce the processing time that is spent in arithmetic computation, a real number is represented using a fraction of integers. In this way, the arithmetic is limited to integer operations, performed by fast combinational circuits. A simple state machine is required to control sums and products of fractions. Sigmoid is used as the activation function in the proposed implementation. It is approximated by polynomials, whose underlying computation requires only sums and products. A theorem is introduced and proven so as to cover the arithmetic strategy of the computation of the activation function. Thus, the arithmetic circuitry used to implement the neuron weighted sum is reused for computing the sigmoid. This resource sharing decreased drastically the total area of the system. After modeling and simulation for functionality validation, the proposed architecture synthesized using reconfigurable hardware. The results are promising.