Reconfigurable hardware for neural networks: binary versus stochastic

Authors:
Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
State University of Rio de Janeiro, Department of Electronics Engineering and Telecommunications, Faculty of Engineering, Rio de Janeiro, Brazil;State University of Rio de Janeiro, Department of Systems Engineering and Computation, Faculty of Engineering, Rio de Janeiro, Brazil
Venue:
Neural Computing and Applications
Year:
2007

Citing 0
Cited 5

Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks

ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs

Neurocomputing
Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks Using Fractional Fixed Point Representation

ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Artificial neural networks in hardware: A survey of two decades of progress

Neurocomputing
Compact yet efficient hardware implementation of artificial neural networks with customized topology

Expert Systems with Applications: An International Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper is focused on hardware implementation of neural networks. We propose a reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. For this purpose, we use field-programmable gate arrays i.e. FPGAs. As the state-of-the-art FPGAs still lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement efficiently the computation performed by a neuron. This paper describes and compares the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time × area classic factor.