The lure of molecular computing
IEEE Spectrum
VLSI implementation of a neural network memory with several hundreds of neurons
AIP Conference Proceedings 151 on Neural Networks for Computing
Scientific American
Analog VLSI and neural systems
Analog VLSI and neural systems
A silicon model of auditory localization
Neural Computation
An electrically trainable artificial neural network (ETANN) with 10240 “Floating Gate” synapses
Artificial neural networks
A systolic array exploiting the inherent parallelisms of artificial neural networks
Microprocessing and Microprogramming
Digital neural networks
Neural network constructive algorithms: trading generalization for learning efficiency?
Circuits, Systems, and Signal Processing - Special issue: networks for neural processing
New algorithms for training feedforward neural networks
Pattern Recognition Letters
A High-Speed Analog Neural Processor
IEEE Micro
Associative neural memories
Machine Learning
Mixed analog/digital matrix-vector multiplier for neural network synapses
Analog Integrated Circuits and Signal Processing - Special issue: selected articles from the 1994 NORCHIP seminar
Special-purpose digital hardware for neural networks: an architectural survey
Journal of VLSI Signal Processing Systems
Image segmentation based on oscillatory correlation
Neural Computation
A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea
Analog Integrated Circuits and Signal Processing
Neuromorphic systems engineering: neural networks in silicon
Neuromorphic systems engineering: neural networks in silicon
Digital VLSI for neural networks
The handbook of brain theory and neural networks
ANNSyS: an analog neural network synthesis system
Neural Networks
A Dedicated Multi-Chip Programmable System for Cellular Neural Networks
Analog Integrated Circuits and Signal Processing - Special issue on Learning on Silicon
Analog Integrated Circuits and Signal Processing
Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
RAM-Based Neural Networks
An Analog VLSI System for Stereoscopic Vision
An Analog VLSI System for Stereoscopic Vision
Parallel Architectures for Artificial Neural Networks: Paradigms and Implementations
Parallel Architectures for Artificial Neural Networks: Paradigms and Implementations
Towards the Visual Microprocessor
Towards the Visual Microprocessor
Cellular Neural Networks: Analysis, Design and Optimization
Cellular Neural Networks: Analysis, Design and Optimization
Pulsed Neural Networks
Cellular neural networks and visual computing: foundations and applications
Cellular neural networks and visual computing: foundations and applications
Spiking Neuron Models: An Introduction
Spiking Neuron Models: An Introduction
On the Performance of Pulsed and Spiking Neurons
Analog Integrated Circuits and Signal Processing
Mixed Mode VLSI Implementation of a Neural Associative Memory
Analog Integrated Circuits and Signal Processing
IEEE Micro
Learning Probabilistic RAM Nets Using VLSI Structures
IEEE Transactions on Computers
Finite Precision Error Analysis of Neural Network Hardware Implementations
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
A Continuous Restricted Boltzmann Machine with a Hardware-Amenable Learning Algorithm
ICANN '02 Proceedings of the International Conference on Artificial Neural Networks
Simulation of Spiking Neural Networks on Different Hardware Platforms
ICANN '97 Proceedings of the 7th International Conference on Artificial Neural Networks
A New Concept for Parallel Neurocomputer Architectures
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
FPGA Implementation of a Neural Network for a Real-Time Hand Tracking System
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A Full-Parallel Digital Implementation for Pre-Trained NNs
IJCNN '00 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 2 - Volume 2
ICAL 2003 Proceedings of the eighth international conference on Artificial life
Optical implementation of the Kak neural network
Information Sciences—Informatics and Computer Science: An International Journal
Modeling Selective Attention Using a Neuromorphic Analog VLSI Device
Neural Computation
Spike-Driven Synaptic Plasticity: Theory, Simulation, VLSI Implementation
Neural Computation
ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy: Research Articles
International Journal of Circuit Theory and Applications - CNN Technology
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Image Processing Using Pulse-Coupled Neural Networks
Image Processing Using Pulse-Coupled Neural Networks
FPGA Implementations of Neural Networks
FPGA Implementations of Neural Networks
Neural Networks: A Comprehensive Foundation (3rd Edition)
Neural Networks: A Comprehensive Foundation (3rd Edition)
Towards cortex sized artificial neural systems
Neural Networks
International Journal of Circuit Theory and Applications
Reconfigurable hardware for neural networks: binary versus stochastic
Neural Computing and Applications
Synaptic Dynamics in Analog VLSI
Neural Computation
CMOL: Second life for silicon?
Microelectronics Journal
Parallelization of cellular neural networks on GPU
Pattern Recognition
Brain-scale simulation of the neocortex on the IBM Blue Gene/L supercomputer
IBM Journal of Research and Development
International Journal of Circuit Theory and Applications - Cellular Wave Computing Architecture
Pattern recognition and reading by machine
IRE-AIEE-ACM '59 (Eastern) Papers presented at the December 1-3, 1959, eastern joint IRE-AIEE-ACM computer conference
Scaling analysis of a neocortex inspired cognitive model on the Cray XD1
The Journal of Supercomputing
Stochastic bitstream-based CNN and its implementation on FPGA
International Journal of Circuit Theory and Applications - CNNA part II
Cmol crossnets as defect-tolerant classifiers
Cmol crossnets as defect-tolerant classifiers
Artificial neural networks: a review of commercial hardware
Engineering Applications of Artificial Intelligence
The Art of Multiprocessor Programming
The Art of Multiprocessor Programming
Reconfigurable hardware evolution platform for a spiking neural network robotics controller
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
A programmable time event coded circuit block for reconfigurable neuromorphic computing
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
A SIMD neural network processor for image processing
ISNN'05 Proceedings of the Second international conference on Advances in neural networks - Volume Part II
Comparative investigation into classical and spiking neuron implementations on FPGAs
ICANN'05 Proceedings of the 15th international conference on Artificial Neural Networks: biological Inspirations - Volume Part I
A silicon synapse based on a charge transfer device for spiking neural network application
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
CMOL crossnets as pattern classifiers
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Digitally programmable analog building blocks for the implementation of artificial neural networks
IEEE Transactions on Neural Networks
Analog implementation of pulse-coupled neural networks
IEEE Transactions on Neural Networks
Implementation of pulse-coupled neural networks in a CNAPS environment
IEEE Transactions on Neural Networks
A neuromorphic VLSI device for implementing 2D selective attention systems
IEEE Transactions on Neural Networks
NeuroPipe-Chip: A digital neuro-processor for spiking neural networks
IEEE Transactions on Neural Networks
A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation
IEEE Transactions on Neural Networks
Implementation issues of neuro-fuzzy hardware: going toward HW/SW codesign
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Guest editorial - Special issue on neural networks hardware implementations
IEEE Transactions on Neural Networks
A digital hardware pulse-mode neuron with piecewise linear activation function
IEEE Transactions on Neural Networks
A compact 3D VLSI classifier using bagging threshold network ensembles
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
A new wide range Euclidean distance circuit for neural network hardware implementations
IEEE Transactions on Neural Networks
Analog implementation of ANN with inherent quadratic nonlinearity of the synapses
IEEE Transactions on Neural Networks
Simple model of spiking neurons
IEEE Transactions on Neural Networks
Scalable closed-boundary analog neural networks
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Lneuro 1.0: a piece of hardware LEGO for building neural network systems
IEEE Transactions on Neural Networks
The Mod 2 Neurocomputer system design
IEEE Transactions on Neural Networks
An analog implementation of discrete-time cellular neural networks
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Adaptive routing strategies for large scale spiking neural network hardware implementations
ICANN'11 Proceedings of the 21th international conference on Artificial neural networks - Volume Part I
A Highly Parallel Multi-class Pattern Classification on GPU
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
Mathematics and Computers in Simulation
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This article presents a comprehensive overview of the hardware realizations of artificial neural network (ANN) models, known as hardware neural networks (HNN), appearing in academic studies as prototypes as well as in commercial use. HNN research has witnessed a steady progress for more than last two decades, though commercial adoption of the technology has been relatively slower. We study the overall progress in the field across all major ANN models, hardware design approaches, and applications. We outline underlying design approaches for mapping an ANN model onto a compact, reliable, and energy efficient hardware entailing computation and communication and survey a wide range of illustrative examples. Chip design approaches (digital, analog, hybrid, and FPGA based) at neuronal level and as neurochips realizing complete ANN models are studied. We specifically discuss, in detail, neuromorphic designs including spiking neural network hardware, cellular neural network implementations, reconfigurable FPGA based implementations, in particular, for stochastic ANN models, and optical implementations. Parallel digital implementations employing bit-slice, systolic, and SIMD architectures, implementations for associative neural memories, and RAM based implementations are also outlined. We trace the recent trends and explore potential future research directions.