Adaptive routing strategies for large scale spiking neural network hardware implementations

Authors:
Snaider Carrillo;Jim Harkin;Liam McDaid;Sandeep Pande;Seamus Cawley;Fearghal Morgan
Affiliations:
Intelligent Systems Research Centre, University of Ulster, Derry, Northern Ireland;Intelligent Systems Research Centre, University of Ulster, Derry, Northern Ireland;Intelligent Systems Research Centre, University of Ulster, Derry, Northern Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group, National University of Ireland Galway,, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group, National University of Ireland Galway,, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group, National University of Ireland Galway,, Galway, Ireland
Venue:
ICANN'11 Proceedings of the 21th international conference on Artificial neural networks - Volume Part I
Year:
2011

Citing 8
Cited 1

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Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers

Neural Networks

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Abstract

This paper presents an adaptive Network-on-Chip (NoC) router, which forms part of an embedded mixed signal Spiking Neural Network (SNN) architecture called EMBRACE (Emulating Biologically-inspiRed ArChitectures in hardware). The novel adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. The router also adapts to NoC traffic congestion or broken NoC connections (faults) by reconfiguring the routing topology to select an alternative route. Performance, power and area analysis of the proposed adaptive router using Synopsys Design Compiler (for TSMC 90nm CMOS technology) indicates a router throughput of 3.2Gbps on each of 5 available router channels, low router power consumption (1.716mW) and small router area (0.056mm2). Router adaptive behaviour in the presence of applied real-time traffic congestion has been demonstrated on a Virtex II Pro Xilinx FPGA for a 4×2 router array. Results indicate the feasibility of using the proposed adaptive NoC router within a scalable EMBRACE hardware SNN architecture.