Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers

Authors:
Snaider Carrillo;Jim Harkin;Liam Mcdaid;Sandeep Pande;Seamus Cawley;Brian Mcginley;Fearghal Morgan
Affiliations:
Intelligent Systems Research Centre (ISRC), University of Ulster, Magee Campus, Londonderry, BT48 7JL, Northern Ireland, United Kingdom;Intelligent Systems Research Centre (ISRC), University of Ulster, Magee Campus, Londonderry, BT48 7JL, Northern Ireland, United Kingdom;Intelligent Systems Research Centre (ISRC), University of Ulster, Magee Campus, Londonderry, BT48 7JL, Northern Ireland, United Kingdom;Bio-Inspired Electronics and Reconfigurable Computing Research Group (BIRC), National University of Ireland, NUI Galway, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group (BIRC), National University of Ireland, NUI Galway, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group (BIRC), National University of Ireland, NUI Galway, Galway, Ireland;Bio-Inspired Electronics and Reconfigurable Computing Research Group (BIRC), National University of Ireland, NUI Galway, Galway, Ireland
Venue:
Neural Networks
Year:
2012

Citing 24
Cited 1

Artificial Neural Networks: A Tutorial

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Signalling techniques and their effect on neural network implementation sizes

Information Sciences: an International Journal
Interconnection Networks: An Engineering Approach

Interconnection Networks: An Engineering Approach
Networks on Chips: A New SoC Paradigm

Computer
Principles and Practices of Interconnection Networks

Principles and Practices of Interconnection Networks
A survey of research and practices of Network-on-chip

ACM Computing Surveys (CSUR)
A GALS Infrastructure for a Massively Parallel Multiprocessor

IEEE Design & Test
Challenges for large-scale implementations of spiking neural networks on FPGAs

Neurocomputing
A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs

ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks

International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Segment gating for static energy reduction in Networks-on-Chip

Proceedings of the 2nd International Workshop on Network on Chip Architectures
Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors

ACSD '09 Proceedings of the 2009 Ninth International Conference on Application of Concurrency to System Design
Tofu: A 6D Mesh/Torus Interconnect for Exascale Computers

Computer
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks

FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Efficient simulation of large-scale spiking neural networks using CUDA graphics processors

IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
An efficient, high-throughput adaptive NoC router for large scale spiking neural network hardware implementations

ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
A world survey of artificial brain projects, Part I: Large-scale brain simulations

Neurocomputing
Artificial neural networks in hardware: A survey of two decades of progress

Neurocomputing
Modeling Spiking Neural Networks on SpiNNaker

Computing in Science and Engineering
Adaptive routing strategies for large scale spiking neural network hardware implementations

ICANN'11 Proceedings of the 21th international conference on Artificial neural networks - Volume Part I
Hardware spiking neural network prototyping and application

Genetic Programming and Evolvable Machines
Simple model of spiking neurons

IEEE Transactions on Neural Networks
Which model to use for cortical spiking neurons?

IEEE Transactions on Neural Networks

Online traffic-aware fault detection for networks-on-chip

Journal of Parallel and Distributed Computing

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Abstract

The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 x 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware.